1. Field of the Invention
Example embodiments of the present invention relate to impedance control circuits and methods of controlling impedance.
2. Description of the Related Art
Related art semiconductor devices may be mounted on, for example, a board (e.g., a printed circuit board (PCB) flexible PCB, etc.). If an impedance of the board is different from that of the semiconductor device(s), data transmitted from the semiconductor devices to the board may become distorted.
A resistor may be positioned outside, and connected to the semiconductor device, and an impedance control circuit may be positioned within the semiconductor device to equalize the impedance of the output driver and the board. The impedance control circuit may be used to adjust the impedance of the resistor.
FIG. 1 is a block diagram illustrating a related art impedance control circuit.
Referring to FIG. 1, the related art impedance control circuit may include a current source (C/S) 110, an impedance adjustment circuit 120, a comparator 160, a thermal code generator (TCG) 130, a control circuit 140, and a register 150.
The current source 110 may be installed in the semiconductor device and may provide a constant, or substantially constant, current level. The impedance control circuit 140 may include a plurality of transistors, which may be connected (e.g., serially connected) to the current source 110. Each gate of the transistors may be connected to the register 150 and the respective transistors may be turned on using data stored in the register 150 as a control signal.
The comparator 160 may compare a reference voltage Vref, generated by a voltage reference circuit (not shown), with a node voltage Vterm, generated at a node between the current source 110 and the impedance adjustment circuit 120, based on an operation mode signal P/D. The operation mode signal P/D may determine the operating mode of a circuit and a clock signal CLOCK.
The thermal code generator 130 may be initialized by a reset signal RESET and may generate a plurality of code values C1i based on an output signal U/D of the comparator 160 and the clock signal CLOCK.
The control circuit 140 may receive the output signal U/D of the comparator 160 and the clock signal CLOCK, count a number of logic value transitions of the output signal U/D of the comparator 160, and generate a complete signal COMPLETE.
The register 150 may generate a plurality of code values C2i, for controlling the transistors in the impedance adjustment circuit 120, based on the code values C1i and the complete signal COMPLETE.
The filters (e.g., low-pass filters) 181 and 182 may remove higher frequency signals in the node voltage Vterm and the reference voltage Vref.
The related art impedance control circuit may further include a latch circuit 170 when the comparator 160 is idle, for example, in response to the operating mode signal P/D, the latch circuit 170 may latch (e.g., store) the output of the comparator 160 for a period of time.
In operation of the related art impedance control circuit, the node voltage Vterm, between the current source 110 and the impedance adjustment circuit 120, may be compared with the reference voltage Vref, for example, based on the operating mode signal P/D output by the comparator 160. If the node voltage Vterm is lower than the reference voltage Vref, the comparator 160 may output a low logic signal ‘L’. The register 150 may latch the code values C1i, which may be may be n bit binary values, generated by the thermal code generator 130.
The code values C2i may be generated, based on the code values C1i, transmitted to the impedance adjustment circuit 120, the number of transistors turned on may be decreased (e.g., in response to the second code values C2i), and the impedance value of the impedance adjustment circuit 120 may be increased. This may increase the node voltage Vterm.
When the node voltage Vterm is greater than the reference voltage Vref, the comparator 160 may output a logic high signal ‘H’, and the register 150 may latch the code values C1i generated by the thermal code generator 130.
The code values C2i may be generated based on the code values C1i, transmitted to the impedance adjustment circuit 120, the number of transistors turned on may be increased (e.g., in response to the code values C2i), and the impedance value of the impedance adjustment circuit 120 may be decreased. This may decrease the node voltage Vterm.
The control circuit 140 may count the number of logic value transitions of the output signal U/D of the comparator 160, and determine a logic value for the control signals C2i such that the node voltage approaches the reference voltage Vref.
FIG. 2 is a waveform diagram illustrating signals of the related art impedance control circuit.
Referring to FIG. 2, when the output signal U/D of the comparator 160 has a low logic level ‘L’, the node voltage Vterm may increase (e.g., stepwise) each clock cycle until the output signal U/D transitions to a logic high signal ‘H’. The output signal U/D may transition to the logic high signal ‘H’, and the node voltage Vterm may be reduced (e.g., stepwise) at the next clock cycle. When the change (e.g., increase or decrease) in the Vterm causes the logic level of output signal U)/D to transition (e.g., from ‘L’ to ‘H’ and/or ‘H’ to ‘L’), for example, in consecutive clock cycles (e.g., continuously), the control circuit 140 may generate the complete signal COMPLETE after a period of time has elapsed.
An on-chip termination element, in an interface (e.g., a high-speed interface), may be coupled to input/output signal lines and may reduce signal reflection. When the on-chip termination element controls (e.g., digitally controls) impedance, a binary counter may be used for counting (e.g., up or down). The code value may vary repeatedly between a code value such that the node voltage Vterm approaching the reference voltage Vref may be generated, and the code value may increase or decrease, for example, by a binary value ‘1’.
FIG. 3 is a waveform diagram illustrating a partially enlarged portion of A in the waveform diagram of FIG. 2.
Referring to FIG. 3, the level of the node voltage Vterm may oscillate between a first level and a second level, and the node voltage Vterm may vary (e.g., asymmetrically) with the reference voltage Vref due to, for example, variations in process, temperature, voltage, etc. Since the node voltages Vterm at clock cycles CLK1 and CLK3 has a level closer to the reference voltage than the voltage level of the node voltage Vterm at a clock cycle CLK2, the node voltage at the clock cycle CLK1 or CLK3 may be selected as a termination voltage. In related art semiconductor devices, determining which voltage level between the first and second levels of the node voltage Vterm is output may not be pre-defined and any arbitrary one of the voltage levels may be output.
The node voltage Vterm closer to the reference voltage Vref may be selected, for example, by increasing the bit number of the code value by, for example, 1. However, a size of an NMOS transistor (e.g., W/L (width to length ratio) of the NMOS transistor) used for the impedance adjustment circuit and a termination resistor may be doubled and a chip size may be increased.